1. "Area, Power, and Pin Efficient Chip I/O using Multi-Bit-Differential
   Signaling"
   University of Pittsburgh and Intelligent Micro Design
   
   This project investigates a new low-power, area and pin efficient alternative to serial differential links for chip-to-chip and backplane signaling. Our technique, called multi-bit-differential-signaling (MBDS), consists of a new design for the driver and link termination network coupled with a novel coding system based on N choose M (nCm) codes.  In an nCm coded MBDS channel there are physical interconnections over which all codes carry exactly m 1-bits. This property gives MBDS links signal to noise and transmission characteristics comparable to low voltage differential signaling (LVDS). Moreover, MBDS is fully compatible with commercial LVDS receivers in point-to-point and multi-point bus topologies. However, because MBDS channels have a higher information density, they use up to 40% less power and up to 33% fewer I/O pads than equivalent LVDS links. In a preliminary study we have implemented and tested MBDS links over 8” of FR4 standard PCB material at 500Mbps.  These links used custom drivers in .5um SiGe transmitting to two types of standard differential receivers: commercial LVDS chips, and SiGe ASICs. This project focuses on the design and fabrication of a new test chip and PCB link to evaluate the performance and noise immunity of the circuits at gigabit rates in 0.18um CMOS. An additional focus is on the architecture of the multi-conductor/multi-layer coupled transmission line structures that will be required for these links. They are investigating, designing and fabricating a number of such structures on the test PCB and evaluating the performance of each with MBDS links.
   
   
2. "On-chip Nuclear Battery based on High-Density Tritium Locking Technology in Semiconductor and Dielectric"
   University of Pittsburgh and Identifi Technologies
   
   This research program proposes to develop on-chip nuclear micro-power sources using high-density tritium locking. This technology is transplanted from the technologies for hydrogen storage, semiconductor processing, and fiber optic device fabrication. We propose to use the combination of high-pressure tritium loading at elevated temperature with rapid thermal cycling and deep ultra-violet laser radiation to permanently lock high density tritium in metal hydride films on silicon chips, dielectric films, amorphous and crystalline semiconductors. We will demonstrate that over 100-mW/cm³, 20-mW/cm³, and 10-mW/cm³ isotope power density in metal hydride films, amorphous/crystalline silicon pn-junctions, and dielectric films, respectively. A number of nuclear-to-electric energy conversion technologies based on thermal voltaic, resonance nuclear battery, silicon p-i-n junctions, and photovoltaic effects will be investigated to convert nuclear energy to electric energy. The goal of this project is to demonstrate a scalable, on-chip, tritium battery with a continuous electric power output >2-µW, energy conversion efficiency > 3%, and a power degradation < 10% per year. On-chip continuous electric power output will be used to power non-volatile RAM, real-time clock circuitries, RFID tags, and intrusion detector with wireless transponders. Using deep UV laser radiation, we will demonstrate that tritium locking in dielectric film can be achieved in an area less than 1-µm²; micron-size tritiated dielectric array on silicon wafer will be demonstrated for on-chip charge embedded technology, high-density data storage, MEMS electrostatic actuation, and on-chip ionization sources.
   
   
3. "Software Techniques for Efficiently Enabling Secure Distributed Storage"
   BitArmor Systems, Pittsburgh, PA
   
   This research program proposes the design and creation of a flexible software toolkit that facilitates the implementation of data storage security systems.  With the toolkit, software developers can more rapidly build solutions that defend the growing value and volume of digital information assets.  Much of the difficulty in providing transparent security for stored data stems from the complexity of interfacing with file systems and operating systems. Furthermore, because of such engineering obstacles, the security features of existing data protection products are often limited and not customizable. The proposed toolkit will efficiently handle complicated OS and file system interactions and implements the cryptographic protocols needed to strongly protect data at rest.  In addition, the toolkit will enable the customization of many security features, including access control policies, user authentication techniques, auditing capabilities, and enforcement mechanisms.  Support will be provided for a variety of standardized encryption algorithms as well as for the use of developer-defined cryptographic operations.  In addition, as a secondary result of this project, we propose the creation of installable secure file system software. This software will demonstrate the utility of the toolkit by enabling the transparent protection of stored file data for users and applications. 
   
   
4. "Asymmetric Security Solutions for Networks of Simple Devices"
   The Pennsylvania State University
   
   Hierarchical RFID networks are becoming widely deployed for both commercial and military applications, for example to track the shipment and warehousing of supplies. Because many of these applications transmit sensitive data, it is an important problem to provide authentication and encryption services in these networks. Given the limited nature of these devices, symmetric key algorithms must be used for authentication and encryption. This requires that any two nodes that must communicate, for example an active RFID tag and a scanner, to share a common key. We propose a system in which few keys are deployed in simple nodes, and a much higher number of keys in the nodes which have more memory. With the proper number of keys deployed, we can achieve the required secure connectivity using limited memory. Our initial results indicate when using a scheme such as this, simple end nodes will require almost an order of magnitude less memory for key storage than other proposed key deployment methods. It also enables much simpler handshaking protocols. This work will fully design and engineer this system, implement the protocols that execute between these simple nodes to establish secure connectivity, and implement the required functions to use these keys for secure communication. Results will include the software libraries for the protocols, and detailed experimental performance evaluation on memory and CPU usage on the end nodes. We expect these results to be direct interest to companies working on RFID technology, sensor platforms, and memory solutions targeted at these platforms.
   
   
5. "High Performance Embedded Model Predictive Control System-on-Chip"
   Lehigh University
   
   This project designs, implements and evaluates an embedded System-on-Chip (SoC) Model Predictive Control (MPC) algorithm. The primary advantage of MPC over traditional proportional-integral-derivative (PID) controllers is its ability to explicitly incorporate a variety of system models, system and controller performance constraints and provide a truly optimal control design with respect to a flexible choice of performance objectives. Systems that can directly benefit from embedded MPC include CD drive controllers, automobile controllers for slip/skid compensation, MEMS gyroscope controllers, microelectronic and digital multimedia controllers, micro-power controllers, numerous aerospace embedded control applications, autonomous biomedical devices that require advanced embedded system-on-chip MPC in implants and biomedical microfluidic devices. For processes with slow dynamics and low sampling rates, MPC is typically implemented on a dedicated computer. For systems with fast dynamics and constrained geometries such as those in MEMS and implantable biomedical devices, hardware embedded MPC system-on-chip would be an appropriate controller implementation since the size and application precludes the use of a dedicated computer. We propose to investigate the development of such an embedded MPC prototype. To our knowledge, no attempt has been made to embed the MPC algorithm on system-on-chip platforms. Currently, Texas Instruments, Motorola and Infineon are attempting to develop a flexible hardware architecture to allow implementation of MATLAB-based controllers on their chips. This clearly indicates the commercial relevance of our project for companies specializing in embedded control systems.
   
   
6. "Transaction Level Power Modeling Methodology Using PCI- Express Core as the Design Driver"
   The Pennsylvania State University
   
   This project will develop a transaction-level power model using PCI-Express as a design driver. In terms of providing I/O connectivity for embedded, desktop and server applications, PCI-Express is emerging as a standard for a unified I/O architecture. In commercial SoC designs, a major portion of overall power consumption can be consumed in the multiple PCI-Express cores required to support multiple devices. Consequently, power estimation and optimization for the PCI-Express core implementation is a very relevant design driver. The techniques developed to estimate power from a TL model can be applied to other IP cores. One deliverable from this project will be a TL model that will model the critical functionality of the PCI-Express core. The key deliverable will be a power modeling technique at the transaction level. Instead of RTL-level power estimation approaches used for the IP cores currently, the TL-power model will associate a power value with each individual transaction. Thus, this approach is more accurate than spreadsheet approaches that just associate a power number with a particular state (e.g., idle, active) while being significantly faster than detailed RTL simulation. A transaction triggers a particular functionality of the core such as CRC generation and flow control provided by the PCI-Express core. The power characterization for every transaction will be created from a RTL implementation of the core and by stressing this model with the sequence of inputs forming this transaction. The required parameters, instead of being statically characterized, will be determined when executing the application and can be used to dynamically change the level of transaction granularity.
   
   
7. "High-Performance RF Design Based on Technology-Independent, Scalable Sub-Circuit Cells"
   Carnegie Mellon University
   
   The design of RF IC is unduly challenging due to the immense complexity of parasitic effects in circuit components and the lack of a formal design methodology. As future wireless standards move towards higher frequencies for more bandwidth, RF circuit tolerance for parasitic is diminishing. At the same time, high-frequency parasitic effects in nanoscale devices are becoming more complicated. Moreover, the increasing cost of photolithography mask set makes design re-spins for tuning RF circuit performance no longer an acceptable option as in older generation technologies. To minimize design cost and reach the ultimate goal of first pass silicon success for RF circuits, we will implement a technology independent sub-circuit cell library in a standard 130-nm CMOS process.
   
   
8. "Real-Time, Low-Power Speech Recognition System-on-a-Chip"
   University of Pittsburgh 
   
   The world-wide market for speech processing technologies is expected to reach $16.3 billion by 2005. While this may be an optimistic prediction, it is clear that there is a large application space for devices that can recognize our spoken words. Current technology enables very simple word recognition for portable devices but is limited to less than a dozen words. This effort will focus on continuous speech for 300 to 1200 words for .command and control applications. Immediate applications are: PDAs, Cells phones, the Sony PlayStation, and the Vocollect TalkMan data collector. This effort will produce a system-on-a-chip device that can be mass produced for a variety of consumer devices. Focusing on small to medium size vocabularies will enable us to also design a small, low power device. This device will be a single SoC that interfaces to an external Flash chip for storage and a single low-power DRAM chip for operation. Hardware search memories are devices that are literally 1,000 times faster than that of conventional memory. We demonstrated the use of these devices during the first phase of this effort and will continue to use them as a model for computation. One of the innovations of the first phase was the creation of a hardware search memory using a standard DRAM when searching a fixed data set like speech models. The final deliverable will be a working SoC design that translates microphone inputs to words. We will demonstrate working hardware on the OKI MicroPlat prototype.
   
   
9. "Multiscale Thermal Modeling of Integrated Systems "
   Carnegie Mellon University
   
   Thermal modeling and management issues span from the individual device level to the system component (e.g. processor) level, thereby representing length scales that range from 10-8 m to 10-2 m. Therefore, the thermal modeling problem is challenged by the difficulty in developing accurate yet cost effective computational capabilities that can be used to guide strategies for proper cooling of the system. This project will combine expertise from two disciplines to advance the thermal modeling and analysis capabilities for integrated systems. First, robust analytical models will be developed to capture the nature of the sub-continuum energy transport at length scales ranging from 10 nm to several microns. From these models we will construct macromodels that can be abstracted to a full system scale model in the form of equivalent thermal RC circuits. At the system scale, we have developed efficient analysis methodologies to perform fast 3D full-system thermal simulation based on the equivalent thermal circuits. We will refine a runtime and memory efficient multilevel simulation methodology based on multi-grid method for this 3D thermal problem. While our approach can be applied for thermal analysis of any integrated system problem, the multi-scale nature of our approach allowed us to consider the impact of thermal effects on the most advanced silicon technologies. For example, we will describe how to analyze the thermal effects of a large full chip model while including the impact of the thermal gradients on the very thin films which comprise the strained SOI silicon devices and copper interconnects.