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  1. "Dynamic, Low Power, Via Patternable Gate Arrays"
    Carnegie Mellon University


    This project will examine variations on our Via-Patterned Gate Array concept that will make their performance and power consumptions be competitive with standard cell ASICs, while retaining the economic advantages of higher yield through regularity, lower NRE, and quicker mask generation time. The two techniques we will examine are via-selected dynamic logic, to increase the performance of critical portions of a VPGA design, and via-selected voltage scaling, to reduce power consumption in non-critical portions of the design.

    Since both innovations require detailed timing analysis, we first need to construct a design flow that will work for VPGAs that has ASIC-quality timing analysis. That flow will be constructed in the first two quarters of the project. The next major milestones are the design of the dynamic cells and the design of the power supply architecture.

  2. "A Circuit Simulation Environment for RF MEMS"
    Carnegie Mellon University


    An RF MEMS modeling and simulation library in the Cadence framework, compatible with SpectreRF will be developed. This library will be designed to enable designers to explore the impact of RF MEMS on front end circuit designs. These models will be developed from the existing NODAS MEMS circuit simulation library, which will also be upgraded to include recently developed models for thermomechanical effects and a large deflection beam model.

  3. "10,000BASE-T Transmission over Standard Category-5 Copper Cable"
    The Pennsylvania State University


    With the increasing popularity of multimedia services supplied over a fixed network, services such as: web browsing, video conferencing and video on demand, it is only a matter of time before users will demand higher bandwidth LAN access. Advances in signal processing and fast CMOS processing power have also made it possible for users to afford high-resolution visual services. IEEE is interested in specifying the next generation 10 Gbps twisted pair Ethernet network (10000BASE-T) in the not too distant future. The funding is requested for conceptual designs and demonstration of a 10,000BASE-T copper transmission system for distribution of a digital signal over ~100 meters of a standard CAT-5 copper cable. We assume it is possible to achieve this using standard CAT-5 copper cable if we adopt vectored transmission on 4 pairs in presence of cross-talk. The 10 Gigabit per second speed is about 1/2 the theoretical capacity on such a cable at 100 meters.