Secure Opportunistic Hotspots (SOHs) are a novel architecture for secure shared use of a wireless local area network (WLAN) by members of the organization that owns the WLAN and visitors from the public at large. Visitors pay for access using an online payment method (e.g. PayPal) at the time of access. SOHs are "opportunistic" because (1) they allow an organization that needs to maintain a WLAN for its members (e.g., home or university) to use it to obtain extra revenues from eventual visitors, and (2) they allow a visitor to use any SOH that may happen to be within range, without requiring the visitor to have any previous or subsequent relationship with that SOH. SOHs allow any of the tens of millions of users with an online payment account to connect to any SOH, which in turn could be any of the millions of existing private, Wi-Fi networks. SOHs may therefore be a significant contribution toward realizing the goal of ubiquitous connectivity. Given SOHs' unique capabilities and blend of features, they can be expected to compete favorably with wireless gateways offered by companies such as ReefEdge and Bluesocket. We have built proof-of-concept implementations of some of SOHs' key innovations. Preliminary results from these implementations include verification that T-Mobile (Starbucks) hotspots are vulnerable to theft of service by session hijacking or freeloading; verification that cookie checking and sequence checking block such attacks and have low overhead; and confirmation that online payment takes little time (7.5 s on average) for paying visitor authentication.

Shopping today largely takes place through online retail stores. Whether one is shopping for clothing, airline tickets, or electronics, one has to contend with long and often variable delays (on the order of tens of seconds) both in browsing and in purchasing. The reason for these delays is poor database architecture. The point is that each request made while shopping results in one or more database queries that must be resolved before a response can be sent to the client, hence the term "dynamically-generated responses." If there were only one client shopping, the database delay would be minimal (10ms). We will present measurements from many real databases showing that regardless of the size of the database and the concurrency level, the bottleneck resource is always lock wait times. That is, most transactions spend most of their time waiting to receive access to a table which is currently locked by some other transaction. Our idea is to focus on certain high-priority requests: requests for expensive items, requests by prior big spenders, requests from clients purchasing QoS agreements. We aim to give these high-priority requests significantly reduced response times by giving them priority over low-priority requests within the lock queues. Our understanding of database internals will allow us to propose new algorithms for prioritization which we expect will be very effective in lowering the response time for high-priority requests, and also lowering overall mean response. Our algorithms will be tested under common general-purpose database implementations and OLTP (online transaction processing) workloads. We will restrict our attention to 3 databases for this project: IBM DB2, PostgreSQL, and Shore, all running on top of Linux. PostgreSQL and Shore are representative of many common databases in how they handle concurrency control, and yet have the added advantage of being open source, which is necessary for us to play with the locking mechanisms.

The goal of this research project is the development of a commercializable process to fabricate ultra-thin quartz resonators. Although resonators with fundamental frequency as large as 1655 MHz have been demonstrated, current quartz resonator manufacturing is limited to fundamental frequencies less than about 225 MHz because of difficulties in reproducibly fabricating ultra-thin, uniform, and reliably electroded resonators, and mechanical difficulties in handling and packaging ultra-thin quartz. The approach described in this proposal avoids both problems by using chemical mechanical polishing (CMP) and wafer bonding to produce ultra-thin quartz resonators with precise dimensional control and simple post process packaging. In addition, the proposed process can be extended to fabricate ultra-thin quartz resonators directly integrated with high performance integrated circuits.

The IEEE is interested in specifying the next generation 10Gbps copper cable Ethernet network, termed 10000BASE-T, in the not too distant future. In search of a proper end-to-end physical-layer design, we are finalizing our proposed system model. This proposal presents conceptual designs of a 10000BASE-T copper transmission system for distribution of a digital signal over ~ 100 meters of a standard CAT-5 copper cable at a transmission rate of 10Gbps. The design makes it possible to achieve this at a target Bit Error Rate (BER) of 10^-10 after equalization and decoding through a turbo (iterative) structure, using standard CAT-5 cable, if we adopt vectored transmission on 4 pairs. Our current design uses a 10-PAM scheme with Decision Feedback Equalization (DFE), in order to increase the date rate to 10Gbps from the current 1Gbps of 1000BASE-T.

Confidentiality and integrity of data are two critical issues for wireless, mobile networks. These issues are of growing importance as wireless service providers attempt to increase wireless data traffic by providing mobile VPN services. The most widely accepted method for ensuring data confidentiality and integrity is to pass encrypted data end-to-end using a mechanism such as IPsec. This model severely limits the types of performance enhancing services that can be provided within a network. In particular, this model is not ideal for the wireless, mobile environment because it makes data transmission less efficient, and it precludes the network from performing many operations that are designed to mitigate the effects of wireless links. This proposal aims at overcoming these problems by using a more flexible security scheme. We base our scheme on the previously proposed Multi-layer IPsec, adding support for key distribution, mobility, and support for several network based performance enhancing services. In this work we start with multi-layer IPsec and extend it significantly to include 1) an efficient key distribution protocol to enable fast session initialization taking into account that multiple security relationships must be established before a session may begin; 2) provisions for fast, secure handoffs that may include new elements that require security associations; 3) provisions for making the security associations dynamic. We will examine the initialization and run-time performance of the system through a combination of experimentation and simulation. In addition, we will examine the performance trade-offs for particular applications, such as video transmission.

The total worldwide market for the voice technologies used to deliver speech recognition-based services is expected to reach nearly $16.3 billion by 2005. While this may be an optimistic prediction, there is little doubt that high-quality automatic speech recognition will eventually become common for commercial and consumer devices. One of the major problems with speech processing is the need to perform a large number of complex searches. The size and complexity of these searches limits the speed and quality of processing. Thus, a highly parallel and sophisticated Speech Search Engine will be a disruptive technology by enabling increased performance while increasing quality. Currently available search memories can search through 16,000 patterns in as little as 10 nanoseconds. On a 2 GHz Pentium, this would require over 80,000 nanoseconds because memory reads are sequential. However, speech processing requires searching for the most likely distribution rather than an exact match. The proposed research will utilize the same parallelism of search memories to implement a search engine specifically designed for speech processing. This effort will accelerate speech processing by integrating a hardware Speech Search Engine within an ARM SOC processor using the Oki microPLAT SOC development system. The Search Engine will attach to the ARM processor through the AMBA high-speed bus (AHB) and will be accessible to the user through a simple software function call executed on the ARM processor. This will drastically improve speech processing capabilities for portable devices.

The problem of characterizing a connector and extracting its SPICE model or S-parameters is extremely important for predicting its electrical performance, in particular for today's increasing data rates. Though modeling and simulation of connectors are important design tools, they must be supplemented by experimental characterization in the final analysis. Two options are available for such characterization: (i) Time domain approach using the Time Domain Reflectometer (TDR); (ii) Frequency Domain measurements utilizing a Vector Network Analyzer (VNA). Of these two, the recent trend is to use the latter because it offers a number of important salutary features for high frequency characterization. This process has many drawbacks, the most important being the fact that the measurements must involve not only the DUT, but a set of calibrating coupons as well, which must be specially designed for this purpose. These calibrating devices are needed to remove the undesired contributions of the text fixtures, for instance the SMA connectors and connecting transmission line traces leading up to the DUT. A novel calibration and de-embedding approach for removing the contribution cables connectors and PWB traces, referred to as the TRL (Thru-Reflect-Line) technique, has been available in the literature for some time, but is designed to handle only two-port structures. In this effort we propose to further examine the TRL technique, on a theoretical basis, and to investigate how the de-embedding technique currently being used for the two-port structures can be extended to the four-port case. A preliminary examination has revealed that the equations that we would now have to solve are highly non-linear in nature and a convenient numerical solution, which is our goal to obtain, may or may not exist.

Today, most chip design tools are flat, and as a result, they have capacity limitations ranging from roughly 1-10M logic gates. Larger designs are assembled in pieces--and the boundaries between these pieces cause problems. Human-created hierarchies are not always optimal, and are sometimes severely sub-optimal. At the top of the wish-list for every CAD tool designer is the desire for robust, high-capacity design techniques that can take such hierarchies and simply flatten them, and then treat the resulting very large design tasks as a flat, all-elements-optimizable design project. We propose to evolve a grid-warping placement engine, to target very large, flat SoC designs. A more mature prototype engine will be constructed, capable of running on network-connected parallel computers. We will work to integrate our placer into a commercial flow, so that our rough layouts can be completed, for careful comparison with industrial designs. We will also work with our proposed industrial partner IBM to target large, next-generation designs to test our tools.

We propose to develop a design tool for magnetic random access memories (MRAMS). The availability of such a design tool will enable the rapid optimization and evolution of the MRAM memory in contrast to prior non-volatile memory technologies that relied more on incremental improvements made over many years of cell iterations. Also, this memory design tool will combine the control of parameters from both the process technologist and the memory designer, which were not historically considered in one environment.

Continuing advances in high-speed digital and analog circuitry, and future Soc assemblies, are placing increasing demands on dielectric substrate materials. Traditional dielectric materials (copper clad laminates made with E-glass reinforcement and epoxy resin) are no longer capable of satisfying the requirements of advanced circuitry. Circuitry designers are increasingly forced to specify exotic and expensive resins, or very costly reinforcement materials, which improve electrical properties, but are very costly and limit design specifications. Dielectric Solutions proposes to develop the next generation woven glass reinforcement that will replace E-glass as the preferred material for high speed digital and advanced analog circuitry. The objective of this research is to identify a cost effective, low dielectric constant (Dk), low dissipation factor (loss) (Df) glass composition that can be formed into fibers and woven into lightweight fabric, which can be then used in standard laminate and PCB processes. Although this new material will be priced at a premium to standard E-glass, the total price-performance relationship of the expected laminate is expected to be favorable to other competing dielectric materials due to lower resin and production costs.