1. "SoC Ink-Jet Printing Technologies for High Performance PVDF Ferroelectric Polymer Micro-Devices"
   The Pennsylvania State University
   
   PVDF based polymers, including the piezoelectric P(VDF-TrFE) (TrFE = trifluoroethylene) copolymers and electrostrictive terpolymers (such as P(VDF-TrFE-CFE), CFE=chlorofluoroethylene), exhibit many electronic properties which have been used and/or are attractive for many applications such as microsensors in MEMS and for IR imaging, data storage and memory devices, gate dielectrics, and microactuators in microfluidic devices for biochips. Since PVDF based polymers are solution processable, inkjet printing and micro-stamping technologies become idea methods for fabricating various devices with high resolution. In this program, we propose to develop the inkjet printing and micro-stamping technologies to produce patterned thin films in thickness down to 0.1 µm which can be used for microelectronics and microdevices. Specifically, we will work with Bridge Semiconductor Corporation in developing inkjet printing and micro-stamping techniques to deposit PVDF based electronic polymers, including copolymers and terpolymers, on Silicon substrates with or without metal coating; a technical report on our research on the optimum parameters for the solutions and fabrication technology for an Infrared Focal Plane Array. Successful development of this program will lead to the commercial development of low cost IR imaging devices, ferroelectric memory for hand held devices, and for gate dielectrics.
   
   
2. "Efficient On-Chip Antennas at GHz Frequencies"
   Carnegie Mellon University and Novocell Semiconductor, Pittsburgh, PA
   
   We propose research in the design trade-offs and experimental verification of selected on-chip antennas, working at a much greater depth on this specific topic than in our initial "CMOS Remote Integrated Sensing Platform" project. The key innovative concept to be explored is the ability to create a synthetic interconnect plane under the antenna that is tuned to have high-impedance at the antenna’s operating frequency.
   
   This idea is inspired by past research on photonic bandgap crystals. Preliminary theoretical calculations show that the multi-level interconnect in modern CMOS can provide the design flexibility to create such planes directly in the IC process. This study will provide verification of the on-chip high-impedance plane with antennas. Engineers from Novocell will design electronics to complete the wireless system-on-chip prototype.
   
   Since on-chip antennas are highly constrained in size, adequate radiation efficiency requires that the power transmission frequency operate at or above 10 GHz. However, high-frequency operation alone does not guarantee efficient antenna coupling. The choice of antenna design is crucial to attaining high efficiency. The radiation efficiency of an antenna is a function of its size, resistance, surrounding loss mechanisms, and the configuration of surrounding dielectric and conducting surfaces. The detailed electromagnetic simulation of several candidate canonical antenna topologies will be undertaken, with the intent to understand the performance constraints and limits for a given topology. The design work will follow with selected experimental verification of the best designs. Our studies will incorporate the practical dimensions and material properties in conventional integrated circuit processes. For promising topologies, a parameterization of key geometric features will prove useful in understanding the impact of these features on efficiency.
   
   
3. "Online Control for Self-Tuning Autonomic Storage Systems"
   The Pennsylvania State University
   
   This project proposes to investigate novel techniques and tools that can be used to design servers to automatically tune themselves to the best configuration at any time and for any given environment. The contributions will be experimentally demonstrated for storage subsystems. Consequently, this project looks to investigate autonomic adaptation of storage subsystems to workload behavior.
   
   This project is expected to make the following unique contributions/deliverables to autonomic server design:
   
   We will build a control theoretic infrastructure where servers can dynamically detect operating conditions (workload and system performance), figure out what (and how much) remedial actions/control need to be taken to modulate its behavior, and reason about how effective this will be (how close to optimal? how fast will it get there? Will the system be stable?).
   
   We will demonstrate an application of this infrastructure to the problem of data shuffling within storage subsystems of a server. The infrastructure will allow dynamic movement of the right data to the right place at the right time, in order to optimize (i) head movements within a single disk, (ii) locality of accesses within a storage area network, and (iii) locality and load balance across the nodes of a cluster. Such data movement/re-positioning in the storage subsystem based on the evolving workload can improve retrieval efficiency.
   
   We will provide a detailed analysis and model of server I/O workload behavior, and make available the source code of our adaptive feedback controller that can be used to develop firmware for disk drives, or to write device drivers in storage area networks, or to design middleware in clustered servers.
   
   
4. "On Demand Macmods for Custom Analog/RF Circuits"
   Carnegie Mellon University
   
   As most large SoCs become mixed-signal designs in the coming decade, we are faced with a serious methodology problem. Analog blocks rarely have good macromodels--simplified models that extract the essential behavior of the design, but simulate quickly enough to allow large systems of such blocks to be connected and simulated in their entirety. The emergence of standard languages (Verilog-AMS, VHDLAMS) and simulation engines provides some of the right infrastructure, but not all of it. A top-level system design can proceed using crude first-order macromodels of the analog blocks: an amplifier can be specified by hand as "a gain" and "a pole" for example. This permits large, complex mixed-signal systems to be simulated efficiently with realistic inputs. The emergence of commercial analog synthesis gives us several paths from each block’s specification to a completed circuit. But this is where the next problem really starts. How will we verify these circuit designs when they are assembled into systems?
   
   We need what are commonly called verification macromodels, which are created bottom-up from transistor designs, and abstract only the essential behaviors. This is very difficult in general and hit-or-miss in practice. There is no single golden macromodel style or strategy. Model structure varies radically with each application.
   
   Today, macromodel design is, in essence, another analog design problem. Each macromodel is a creative mathematical or circuit template that captures some essential behaviors, and jettisons the others. It can be parameterized using curve-fitting techniques. There are standard models for some well-known circuits, e.g., opamps, but not for all circuits, especially novel circuits. The fact that we must design a new model and fitting methods for each new end-application is, we believe, a showstopper for analog methodology. General mathematical techniques to extract arbitrary nonlinear models from arbitrary circuits are in their infancy today. We propose to investigate how the use of recently developed data mining techniques for high-dimensional nonlinear regression may be applied to this pressing problem. Our goal is to create and fit "on demand" macromodel templates that can be correctly configured to match a given time-domain transistor-level circuit. We have successfully applied similar techniques to problems of modeling large populations of circuit data generated by analog synthesis. We propose to extend these ideas to the entirely new application of building simulation models.
   
   
5. "OPNET Modeling and Simulation of a Payload and Protocol Agnostic Switch Router"
   Accipiter Systems, Inc., Wexford, PA
   
   This proposed research develops models for a high capacity, payload and protocol agnostic switch router node, and then simulates MPLS running on a network built from these switch router nodes. The tool of choice to perform these simulations is the tool suite from OPNET Technologies, Inc. OPNET offers a modeling and simulation product for network R&D. This tool enables designers to evaluate how networking equipment, technologies and protocols will perform under simulated network conditions. The specific tool being used is OPNET Modeler. OPNET Modeler is the industry's leading network technology development environment, allowing for the design and study of communication networks, devices, protocols, and applications. The world's most prestigious organizations use Modeler to accelerate the R&D process.
   
   MPLS (Multiprotocol Labeled Switching) will be the protocol used to facilitate the simulation of the models. MPLS combines the properties of virtual circuits common in switch architectures with IP datagrams common in router architectures. MPLS combines the concepts of switching and routing. MPLS-enabled routers forward packets using short, fixed-length labels, which have local significance, through a forwarding paradigm called label swapping.
   
   The deliverables include the simulation models for a high capacity switch router. These models include the policing, shaping, and queuing scheduler of the switch router. OPNET models exist for smaller switches such as the ASX-1000, ASX-4000, and Catalyst 4506 which are 10, 40 and 64 Gbps switches. This research develops models for switch technology that is an order of magnitude larger than these switches. The project deliverables also include a simulation design document, simulation problems encountered and their resolution, and the simulation results.
   
   
6. "Support for Large-Scale Collaborative Applications"
   Carnegie Mellon University
   
   Unfortunately, building high-performance, large-scale, distributed applications on the Internet has been a daunting task. Efforts at making distributed applications easier to develop have concentrated on providing new communication primitives. For example, early efforts to enable such applications relied on IP Multicast, which proved difficult to deploy for a number of reasons, and others incorporated unscalable algorithms, such as flooding. More recent efforts have begun exploring the use of overlays and distributed hash tables (DHTs) to build distributed applications. Unfortunately, scalability issues with overlay designs and the inflexibility of DHTs have made it difficulty to support many distributed applications with these primitives.
   
   In this proposal, we describe tools and techniques that we believe will help in developing a large-scale distributed collaborative application. The key deliverables of this research will be the software artifacts created, including: 1) a large-scale distributed multiplayer game, 2) a distributed publish-subscribe middleware library, and 3) a middleware library that performs object-oriented state management for distributed applications.
   
   While the novel tools and techniques developed part of this proposal focus on supporting collaborative applications, these software tools will have an impact on the development of a much wider variety of large-scale distributed applications. For example, the proposed publish-subscribe system incorporates techniques that can enable scalable, rich queries on a P2P file sharing application. The results of this project will have significant impact on the design and creation of distributed applications used in industry such as auctions (Ebay), inventory databases (Amazon, Sabre), distributed simulation/analysis (GRID, SETI@Home), and scientific visualization.
   
   
7. "Low-Cost CMOS-Compatible Thermal Isolation of Microsystems"
   Carnegie Mellon University
   
   This project will model, demonstrate, and develop fabrication recipes for the use of emerging dielectric materials to manage thermal performance in microelectronic systems. Such materials, specifically those featuring porous silica-based morphologies, have received significant attention in recent years due to their low dielectric constant (k). However, their inherently low thermal conductivity has not been studied in the context of thermal management at the device level. We will consider three specific applications of the technology relevant to Greenhouse member companies: 1) a high precision, temperature stabilized voltage reference, 2) a micro-miniature oven controlled crystal oscillator (OCXO), and 3) an infrared focal plane array (IRFPA). Low-cost, CMOS-compatible, low conductivity materials could significantly improve performance while reducing the power requirement of each application. We will also apply the work to emerging technologies of interest to PDG members in the fuel cell and micro-sensors industries.
   
   The program will be divided into two main tasks: 1) material characterization and process development (75% effort) and 2) system modeling and correlations (25% effort). It is designed to demonstrate the feasibility of aerogel as thermal insulation in CMOS microsystems and apply the work to specific applications of interest to PDG members through system modeling. By demonstrating the building blocks necessary to integrate the material into existing microsystems and developing the computational tools for predictive simulation of aerogel films, we will maximize the program’s relevance and value to PDG members.
   
   
8. "Adaptive Design Debug and Failure Diagnosis"
   Carnegie Mellon University
   
   Diagnosis is a key component of yield learning, where failing parts are thoroughly analyzed to debug the design and tune the manufacturing process. In future technologies, yield learning is expected to become extremely important, thus making the role of diagnosis much more significant. We believe fault tuples can greatly enhance the diagnosis process. Fault tuples are simple constraints on circuit behavior whose combination allows us to exactly model many complex types of design marginalities and defects. Because fault tuples are not tied to any particular error model or defect type, locating and characterizing a circuit failure can be much more precise and efficient.
   
   We propose to develop a diagnosis methodology and associated software for performing adaptive diagnosis using fault tuples. In adaptive diagnosis, the failure is initially modeled using fault tuples. The validity of the model is then compared with available test results. Any mismatch between the model and the test results is then used to adapt the fault tuple model of the failure. This process can be repeated until the model exactly matches the test results or the level of confidence desired in the fault tuple model is satisfied. We believe this approach can be completely automated, making adaptive diagnosis both accurate and efficient. In a two-year effort supported by the PDG, we would develop the methodology and associated software for adaptive diagnosis and show its effectiveness using real designs.
   
   
9. "Expanding Commercial Applications of Xenon Difluoride Etching"
   Xactix, Inc., Pittsburgh, PA
   
   Xenon difluoride (XeF2) is an ideal fabrication technology for creating MEMS SoCs. It overcomes significant barriers to reducing the cost of manufacture, improving the performance of many MEMS devices and integrating MEMS devices with electronics. In addition, XeF2 can be used in other applications beyond MEMS, one significant application in particular is highly selective wafer thinning.
   
   Xenon difluoride silicon etch is already being used by early adopters in the display, aerospace, consumer electronics, networking and automotive industries. Possible benefits to existing PDG member companies are improved processes for manufacturing disk drive heads (Seagate), power transistors (Fairchild), infrared MEMS (Bridge Semiconductor), optical MEMS (Benchmark Photonics) and MEMS displays (Sony). Both Carnegie Mellon University and Penn State University use xenon difluoride to fabricate MEMS devices. Other local MEMS cluster companies which would benefit are Verimetra (Medical Devices) and Akustika (Acoustic MEMS).
   
   In the proposed program XACTIX will address process improvements important for widespread adoption of xenon difluoride silicon etching. Specifically, we will thoroughly explore controlling the uniformity (% variation of etch rate across the wafer), controlling the surface roughness of silicon after etching within commercially viable parameters, controlling the attack on silicon nitride, and understanding XeF2’s effect on new materials for improving MEMS and electronic devices.
   
   
10. "Ultra Compact Temperature Stabilized Crystal Oscillator for Low Noise Clock Generation"
    The Pennsylvania State University
    
    We will demonstrate a new approach to high-precision reference frequency crystal oscillators that we believe will lead to the world’s most compact oven controlled crystal oscillator (OCXO). One result of our previous "quartz crystal on chip" research project (funded by Pittsburgh Digital Greenhouse) is that we were able to position an active quartz crystal resonator region as close as 40um to a silicon substrate or other surface. Using this as a foundation, we have now developed a "chip on crystal" approach to construct extremely compact, low-power, and extremely stable crystal oscillators.

New approach:

1. Micro-scale quartz crystal mesa design using MEMS like process, world’s smallest active mesa area with very low stress 2. Quartz crystal mesa sandwiched between CMOS chip and quartz substrate, provides 1st hermetic seal for the active quartz mesa 3. Diffusion bonded chip and quartz; epoxy free mounting and sealing 4. Integrated heater, temperature sensor, and temperature controller on a single chip close mounted to quartz resonator 5. 2nd hermetic seal provided by primary device package.

Advantages of the new approach include:

1. Smallest packaged OCXO design (~ 0.05 cm³  or less) 2. Low power OCXO due to smaller heated volume and surface area 3. Reduced warm-up time 4. Reduced quartz crystal aging (rate and total) 5. Improved quartz crystal temperature stabilization and/or compensation by use of multiple heaters and temperature controllers close mounted to crystal, also temperature control and temperature compensation can be used together 6. Improved reliability and manufacturability 7. Significant (> ×2) cost reduction of OCXO product

We will provide PDG member companies with the design files for the OCXO chip and quartz crystal mesa, and prototype OCXO units.